Here is a list of instructions and opcodes used by MC88100.

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Last updated : 23.03.1996 at 14:00:00 GTM+1

Table of contents

Instructions and opcodes

Main Instructions



Name Regs Opcode Description
ADD rD,rS,rT 111101dddddsssss011100io000ttttt Integer Add
ADD rD,rS,IMM16 011100dddddsssssmmmmmmmmmmmmmmmm Integer Add
ADDU rD,rS,rT 111101dddddsssss011000io000ttttt Unsigned Integer Add
ADDU rD,rS,IMM16 011000dddddsssssmmmmmmmmmmmmmmmm Unsigned Integer Add
AND rD,rS,rT 111101dddddsssss01000c00000ttttt Logical And
AND rD,rS,IMM16 01000udddddsssssmmmmmmmmmmmmmmmm Logical And
BB0 B,rS,D16 11010nbbbbbsssssdddddddddddddddd Branch On Bit Clear
BB1 B,rS,D16 11011nbbbbbsssssdddddddddddddddd Branch On Bit Set
BCND C,rS,D16 11101ncccccsssssdddddddddddddddd Conditional Branch
BR D26 11000ndddddddddddddddddddddddddd Unconditional Branch
BSR D26 11001ndddddddddddddddddddddddddd Branch to Subroutine
CLR rD,rS,rT 111101dddddsssss10000000000sssss Clear Bit Field
CLR rD,rS,WO 111100dddddsssss100000wwwwwooooo Clear Bit Field
CMP rD,rS,rT 111101dddddsssss01111100000ttttt Integer Compare
CMP rD,rS,IMM16 011111dddddsssssmmmmmmmmmmmmmmmm Integer Compare
DIV rD,rS,rT 111101dddddsssss01111000000ttttt Signed Integer Divide
DIV rD,rS,IMM16 011110dddddsssssmmmmmmmmmmmmmmmm Signed Integer Divide
DIVU rD,rS,rT 111101dddddsssss01101000000ttttt Unsigned Integer Divide
DIVU rD,rS,IMM16 011010dddddsssssmmmmmmmmmmmmmmmm Unsigned Integer Divide
EXT rD,rS,rT 111101dddddsssss10010000000ttttt Extract Signed Bit Field
EXT rD,rS,WO 111100dddddsssss100100wwwwwooooo Extract Signed Bit Field
EXTU rD,rS,rT 111101dddddsssss10011000000ttttt Extract Unsigned Bit Field
EXTU rD,rS,WO 111100dddddsssss100110wwwwwooooo Extract Unsigned Bit Field
FF0 rD,rS 111101ddddd0000011101100000sssss Find First Bit Clear
FF1 rD,rS 111101ddddd0000011101000000sssss Find First Bit Set
INT rD,rS 100001ddddd000000100100tt00sssss Round Floating Point to Integer
JMP rS 111101000000000011000n00000sssss Unconditional Jump
JSR rS 111101000000000011001n00000sssss Jump to Subroutine
LD rD,rS,rT 111101dddddsssss00pptt0u000sssss Load Register from Memory
LD rD,rS[rT] 111101dddddsssss00pptt1u000ttttt Load Register from Memory
LD rD,rS,IMM16 00ppttdddddsssssmmmmmmmmmmmmmmmm Load Register from Memory
LDA rD,rS[rT] 0011ttdddddsssssiiiiiiiiiiiiiiii Load Address
LDA rD,rS[rT] 111101dddddsssss0011tt00000ttttt Load Address
LDA rD,rS[rT] 111101dddddsssss0011tt10000ttttt Load Address
LDCR rD,crS 100000ddddd0000001000ssssss00000 Load from Control Register
MAK rD,rS,rT 111101dddddsssss10100000000sssss Make Bit Field
MAK rD,rS,WO 111100dddddsssss101000wwwwwooooo Make Bit Field
MASK rD,rS,IMM16 01001udddddsssssmmmmmmmmmmmmmmmm Logical Mask Immediate
MUL rD,rS,rT 111101dddddsssss01101100000ttttt Integer Multiply
MUL rD,rS,IMM16 011011dddddsssssmmmmmmmmmmmmmmmm Integer Multiply
NINT rD,rS 100001ddddd000000101000tt00sssss Floating Point Round to Nearest Integer
OR rD,rS,rT 111101dddddsssss01011c00000ttttt Logical Or
OR rD,rS,IMM16 01011udddddsssssmmmmmmmmmmmmmmmm Logical Or
ROT rD,rS,rT 111101dddddsssss10101000000sssss Rotate Register
ROT rD,rS,O 111100dddddsssss10101000000ooooo Rotate Register
RTE   11110100000000001111110000000000 Return from Exception
SET rD,rS,rT 111101dddddsssss10001000000ttttt Set Bit Field
SET rD,rS,WO 111100dddddsssss100010wwwwwooooo Set Bit Field
ST rD,rS,rT 111101dddddsssss0010tt0u000ttttt Store Register to Memory
ST rD,rS[rT] 111101dddddsssss0010tt1u000ttttt Store Register to Memory
ST rD,rS,IMM16 0010ttdddddsssssmmmmmmmmmmmmmmmm Store Register to Memory
STCR rS,crD 10000000000sssss10000ddddddttttt Store to Control Register
SUB rD,rS,rT 111101dddddsssss011101io000ttttt Integer Subtract
SUB rD,rS,IMM16 011101dddddsssssmmmmmmmmmmmmmmmm Integer Subtract
SUBU rD,rS,rT 111101dddddsssss011001io000ttttt Unsigned Integer Subtract
TB0 B,rS,VEC 111100bbbbbsssss1101000vvvvvvvvv Trap On Bit Clear
TB1 B,rS,VEC 111100bbbbbsssss1101100vvvvvvvvv Trap On Bit Set
TBND rS,rT 11110100000sssss11111000000ttttt Trap On Bounds Check
TBND rS,IMM16 11111000000sssssmmmmmmmmmmmmmmmm Trap On Bounds Check
TCND C,rS,VEC 111100cccccsssss1110100vvvvvvvvv Conditional Trap
TRNC rD,rS 100001ddddd000000101100tt00sssss Truncate Floating Point to Integer
XCR rD,rS,crS/D 100000dddddsssss11000rrrrrrttttt Exchange Control Register
XMEM rD,rS,rT 111101dddddsssss0000tt0u000ttttt Exchange Register with Memory
XMEM rD,rS[rT] 111101dddddsssss0000tt1u000ttttt Exchange Register with Memory
XMEM rD,rS,IMM16 0000ttdddddsssssmmmmmmmmmmmmmmmm Exchange Register with Memory
XOR rD,rS,rT 111101dddddsssss01010c00000ttttt Logical Exclusive Or
XOR rD,rS,IMM16 01010udddddsssssmmmmmmmmmmmmmmmm Logical Exclusive Or

Co-processor instructions :


Name Regs Opcode Description
FADD rD,rS,rT 100001dddddsssss00101ffgghhttttt Floating Point Add
FCMP rD,rS,rT 100001dddddsssss00111ffgg00ttttt Floating Point Compare
FDIV rD,rS,rT 100001dddddsssss01110ffgghhttttt Floating Point Divide
FLDCR rD,fcrS 100000ddddd0000001001ssssss00000 Load from Floating Point Control Register
FMUL rD,rS,rT 100001dddddsssss00000ffgghhttttt Floating Point Multiply
FSTCR rS,fcrD 10000000000sssss10001ddddddttttt Store to Floating Point Control Register
FSUB rD,rS,rT 100001dddddsssss00110ffgghhttttt Floating Point Subtract
FXCR rD,rS,fcrX 100000dddddsssss11001xxxxxxttttt Exchange Floating Point Control Register

Further Reading :