Suffix rules

To simplify a Makefile, there is a special kind of rule syntax known as a suffix rule. This is a wildcard pattern that can match targets. Our first Makefile used some. Here is one:

.c.o: $(CC) $(CFLAGS) -c $< -o $@

Unless a more specific rule matches the target being sought, this rule will match any target that ends in .o. These files are said to always be dependent on .c. With some background material now presented, let's take a look at these tools in use.